1. Technical Field of the Invention
The present invention generally relates to silicon-on-insulator (SOI)-based integrated circuits. More particularly, and not by way of any limitation, the present invention is directed to a method and apparatus for mitigating the xe2x80x9chistory effectxe2x80x9d in an SOI-based sense amplifier latch circuit.
2. Description of Related Art
Several semiconductor manufacturers are exploring the possibility of utilizing silicon-on-insulator (SOI) process technology for advanced value-added products such as microprocessors. It is well known that at current 0.18 micron design rules and beyond, the SOI process offers significant advantages over bulk silicon processes widely in use today. Typically, SOI circuits can deliver a 20% performance gain by running at faster speeds because SOI effectively eliminates junction capacitance. Further, as noise margins are improved, signal sensitivity is also enhanced considerably in SOI-based circuitry.
SOI insulates transistors by building them on a silicon film atop a buried layer of oxide (SiO2) across an entire wafer. Until recently it has been considered an attractive but difficult technology. Implanting a layer of oxide typically takes several hours on an expensive implantation machine, and bonding a silicon wafer with an insulating substrate is also quite costly. Further, SOI wafers can suffer from relatively frequent stress-induced defects in silicon, and from pinholes that occur in the buried oxide. Beyond the physical infrastructure, SOI is equally challenging to circuit designers. Drawing the much-vaunted performance gains from SOI requires new electronic design automation (EDA) tools, SOI-specific circuit models and retraining design teams.
An SOI device is insulated on all directions by oxide, on the right and left by shallow trench isolation and on the bottom by the buried-oxide layer in the SOI wafer. The active area of the transistor is a very small silicon volume that is said to xe2x80x9cfloatxe2x80x9d because it is not directly connected to anything. Accordingly, lacking an ohmic contact to ground, the potential floats between the top layer and the buried oxide. And with limited connections through source and drain, but no direct contact, the body voltage can change, giving rise to the floating-body or body bias effect, as well as a number of other issues, such as changes in the breakdown voltage, variable threshold voltages, etc. Further, SOI transistors exhibit what is known as the xe2x80x9chistory effect,xe2x80x9d where the body bias accumulates over time and deteriorates the device switching speed to unacceptable levels.
It should be appreciated by one skilled in the art that these negative xe2x80x9cside effectsxe2x80x9d are particularly detrimental in high-speed data receiver circuitry typically employed in microprocessors, where sense amplifier and latch circuits are implemented for sensing data provided by off-chip input/output (I/O) circuitry. Current solutions that address these issues, such as implementing a separate body contact, are expensive and not entirely satisfactory.
Accordingly, the present invention advantageously provides a method and apparatus for mitigating the history effect in silicon-on-insulator (SOI)-based circuitry, e.g., data interface circuitry operable as a single-ended off-chip signal receiver in a VLSI component such as a microprocessor. In one aspect of the present invention, the exemplary data interface circuitry is comprised of a sense amplifier (sense amp) latch circuit arrangement which includes a sense amp operable to sense data and a latch operable to hold the sensed data. When data is available from an off-chip data I/O circuit, the sense amp generates a pair of complementary data signals responsive to a rising edge in the clock signal. A control signal is used for alternating the sense amp""s operation between an evaluation phase and an equilibration (i.e., pre-charging) phase. A feedback circuit portion is included to effectuate a self-timed loop operable to modify the control signal""s logic state within a clock phase associated with the clock signal provided to the interface circuitry. Since the equilibration phase is entered combinationally off the evaluation phase, both evaluation and equilibration can be triggered from the same clock edge. In a preferred exemplary embodiment, a pair of complementary clocks are provided such that two rising edges are available within a single clock cycle.
In another aspect, the present invention is directed to a data operation method involving the SOI-based circuitry. Responsive to a logic transition in a first clock, a data value is sensed by a sense amp in its evaluation phase. Thereafter, the evaluation phase is shut down so as to enter into an equilibration phase while the first clock is still in the transitioned state. Responsive to a logic transition in a second clock, a next data value is sensed by the sense amp. Subsequently, the sense amp""s evaluation phase is shut down so that the equilibration phase starts while the second clock is still in the transitioned state. By reducing the time spent by the sense amp circuitry in the evaluation phase (wherein the circuitry is in an electrically imbalanced state), the mismatching of accumulated transistor body bias in the SOI devices used in the circuitry is advantageously reduced also.
In a presently preferred exemplary embodiment of the present invention, a pair of inverters provided in the data interface circuitry invert the complementary data signals generated by the sense amp during its evaluation phase. The feedback circuit portion includes an exclusive-OR (XOR) gate which receives the inverted data signals. A pair of zero catcher circuits are included for capturing a high-to-low transition that signifies a substantial completion of the sense amp""s data sensing operation in a particular clock phase associated with one of the two complementary clocks. A multiplexer is provided for propagating a logic low state to the control signal when one of the zero catcher circuits generates a logic low in a particular clock phase so as to shut down the sense amp""s evaluation phase.